STA016A |
RFQ for STA016A Required Field |
 |
| Technical/Catalog Information | STA016A |
| Vendor | STMicroelectronics |
| Category | Integrated Circuits (ICs) |
| Type | Audio Decoder |
| Applications | Multimedia |
| Mounting Type | Surface Mount |
| Package / Case | 64-TQFP |
| Voltage - Supply, Analog | - |
| Voltage - Supply, Digital | - |
| Packaging | Tray |
| Drawing Number | * |
| Lead Free Status | Lead Free |
| RoHS Status | RoHS Compliant |
| Other Names | STA016A STA016A |
| Product | Manufacturers | Pack | D/C |
| STA016A | - | QFP-64 | 01+ |
The STA016A is a single chip MPEG 1, 2 and 2.5 Layer III audio decoder with embedded CDROM decoding capability. It can be easily connected to most existing CDDSP devices via a software configurable serial link. A tipical application block diagram is show in Figure 1. The audio sources, for instance could be an external flash memory.
A useful bypass mode allow using this device also as an audio processor for volume and tone controls.
Typical Application |
Features |
| · AUDIO CD PLAYERS· MULTIMEDIA PLAYERS· CD-ROM PLAYERS· CAR RADIO PLAYERS | ` SINGLE CHIP MPEG LAYER 3 DECODER SUPPORTING: All features specified for Layer III in ISO/IEC 11172-3 (MPEG 1 Audio) All features specified for Layer III in ISO/IEC13818-3.2 (MPEG 2 Audio) Lower sampling frequencies syntax extension,(not specified by ISO) called MPEG 2.5` DECODES LAYER III STEREO CHANNELS,DUAL CHANNEL, SINGLE CHANNEL (MONO)` SUPPORTING ALL THE MPEG 1 & 2 SAMPLING FREQUENCIES AND THE EXTENSION TO MPEG 2.5:48, 44.1,32,24,22.05, 16, 12,11. 025, 8 KHz` ACCEPTS MPEG 2.5 LAYER III ELEMENTARY COMPRESSED BITSTREAM WITH DATA RATE FROM 8 Kbit/s UP TO 320Kbit/s` BYPASS MODE FOR EXTERNAL AUXILIARY AUDIO SOURCE` EMBEDDED ISO9660 LAYER FOR FILESYSTEM DECODING (JOLIET)` EMBEDDED CD-ROM DECODER BLOCKS INCLUDING ECC/EDC CAPABILITY` FLEXIBLE I2S INPUT INTERFACE FOR EASY CONNECTION WITH MOST CD-SERVO DEVICES` EMBEDDED BROWSING COMMAND INTERPRETER FOR EASY FILE-SYSTEM BROWSING` CUE-SHEET CAPABILITY UP TO 100 ENTRIES` BROWSER COMMAND INTERPRETER (BCI) Parent Dir Enter Dir Previous Entry Next Entry Get Record Infos` EASY PROGRAMMABLE GPSO INTERFACE (MONO/STEREO) FOR ENCODED DATA UP TO 5Mbit/s` DIGITAL VOLUME` BASS & TREBLE CONTROL` SERIAL BITSTREAM INPUT INTERFACE` EASY PROGRAMMABLE ADC INPUT INTERFACE` SERIAL PCM OUTPUT INTERFACE (I2S AND OTHER FORMATS)` PLL FOR INTERNAL CLOCK AND FOR OUTPUT PCM CLOCK GENERATION` CRC CHECK AND SYNCHRONISATION ERROR DETECTION WITH SOFTWARE INDICATORS` I2C CONTROL BUS` LOW POWER 2.4V CMOS TECHNOLOGY WITH 3.3V TOLERANT AND CAPABLE I/O |
| Symbol | Parameter |
Value |
Unit |
| VDD | Digital Power Supply at 2.5V (nominal) |
-0.5 to 3.3 |
V |
| VCC | Digital Power Supply at 3.3V (nominal) |
-0.5 to 4 |
V |
| PLL-VCC | Analog Supply Voltage at 2.5V (nominal) |
-0.5 to 3.3 |
V |
| VIH/VIL | Voltage on input pins (3.3V pads) |
-0.5 to VCC +0.5 |
V |
| Tstg | Storage Temperature |
-40 to 150 |
|
| Top | Operative ambient temp |
-40 to +85 (*) |
|
| Tj | Operating Junction Temperature |
-40 to +125 |
